The FIFO register is a write only register. This register is used to control the FIFO (First In / First Out) buffers set to 16550's and higher.

Bit 0 allows the operations with the buffer. Placing '0' into this bit switches off all read/write buffer operations, thus you lose all the data saved in FIFO buffers.

Bits 1 and 2 control the clearing of in and out buffers. Bit 1 is responsible for the in-buffer, while bit 2 is responsible for the out-buffer. Setting these bits to 1 results in clearing the FIFO buffer and doesn't concern shift registers. These two bits are self-dumping so you needn't set them into 0 when the dump is finished.

Bit 3 allows DMA mode selection, this mode is available at 16550 UARTs and above.

Bits 4 and 5 are reserved, also bit 5 is used to switch on the 64-bit FIFO buffer (only for 16750).

Bits 6 and 7 are used to set the triggering level on the Receive FIFO. E.g., if bit 7 was set to 1 and bit 6 to 0, the trigger level is set to 8 bytes. When the FIFO in-buffer receives 8 bytes of data FIFO, then the Received Data Available interrupt is set. See (IIR).